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1 copyright ? cirrus logic, inc. 2004 (all rights reserved) cirrus logic, inc. www.cirrus.com cs8405a 96 khz digital audio interface transmitter features complete eiaj cp1201, iec-60958, aes3, s/pdif-compatible transmitter +5.0 v digital supply (vd+) +3.3 v or 5.0 v digital interface (vl+) on-chip channel status and user bit buffer memories allow block-sized updates. flexible 3-wire serial digital audio input port up to 96 khz frame rate microcontroller write access to channel status and user bit data on-chip differential line driver generates crc codes and parity bits standalone mode allows use without a microcontroller general description the cs8405a is a monolithic cmos device which en- codes and transmits audio data according to the aes3, iec60958, s/pdif, or eiaj cp1201. the cs8405a ac- cepts audio and digital data, which is then multiplexed, encoded, and driven onto a cable. the audio data is input through a configurable, 3-wire in- put port. the channel status and user bit data are input through an spi or i2c microcontroller port, and may be assembled in block-sized buffers. for systems with no microcontroller, a standalone mode allows direct access to channel status and user bit data pins. target applications include a/v receivers, cd-r, dvd receivers, digital mixing consoles, effects processors, set-top boxes, and computer or automotive audio systems. ordering information cs8405a-cs 28-pin soic -10 to +70c cs8405a-cz 28-pin tssop -10 to +70c cs8405a-czz, lead free 28-pin tssop -10 to +70c cs8405a-is 28-pin soic -40 to +85c cs8405a-iz 28-pin tssop -40 to +85c cdb8415a evaluation board i serial audio input misc. control aes3 s/pdif encoder c&ubit data buffer control port & registers output clock generator rxp ilrck isclk sdin txp txn rst omck utcblsda/ cdout scl/ cclk ad1/ cdin ad0/ cs int vl+ dgnd driver ad2 h/s vd+ aug ?04 ds469f2
cs8405a 2 ds469f2 table of contents 1. characteristics and specifications ................ ........................................................ 4 specified operating conditions ................................................................................. 4 absolute maximum ratings ........................................................................................... 4 dc electrical characteristics................................................................................... 5 digital input characteristics ..................................................................................... 5 digital interface specifications................................................................................ 5 transmitter characteristics ..................................................................................... 5 switching characteristics .......................................................................................... 6 switching characteristics - serial audio ports................................................. 6 switching characteristics - control port - spi mode...................................... 8 switching characteristics - control port - i2c mode....................................... 9 2. typical connection diagram ...................................................................................... 10 3. general description ..................................................................................................... 11 3.1 aes3 and s/pdif sta ndards documents ........................................................................ 11 4. three-wire serial input audio port ........................................................................ 11 5. aes3 transmitter .......................................................................................................... .. 13 5.1 transmitted frame and channel status boundary timing .............................................. 13 5.2 txn and txp drivers ...................................................................................................... 1 3 5.3 mono mode operation ..................................................................................................... 13 6. control port description and timing .................................................................... 15 6.1 spi mode .................................................................................................................. ....... 15 6.2 i2c mode .................................................................................................................. ........ 15 6.3 interrupts ................................................................................................................ .......... 16 7. control port register summary ........................................................................... 17 7.1 memory address pointer (map) ....................................................................................... 17 8. control port register bit definitions .................................................................. 18 8.1 control 1 (01h) ............................................................................................................ ...... 18 8.2 control 2 (02h) ............................................................................................................ ...... 18 8.3 data flow control (03h).................................................................................................... 19 8.4 clock source control (04h)............................................................................................... 19 8.5 serial audio input port data format (05h)........................................................................ 20 8.6 interrupt 1 status (07h) (read only)................................................................................. 21 8.7 interrupt 2 status (08h) (read only)................................................................................. 21 8.8 interrupt 1 mask (09h)..................................................................................................... .. 21 8.9 interrupt 1 mode msb (0ah) and interrupt 1 mode lsb (0bh) ......................................... 22 8.10 interrupt 2 mask (0ch) .................................................................................................... 22 8.11 interrupt 2 mode msb (0dh) and interrupt mode 2 lsb (0eh)....................................... 22 8.12 channel status data buffer control (12h) ...................................................................... 23 8.13 user data buffer control (13h) ....................................................................................... 23 8.14 channel status bit or user bit data buffer (20h - 37h) ................................................... 24 8.15 cs8405a i.d. and version register (7fh) (read only) ................................................. 24 9. pin description - software mode .......................................................................... 25 10. hardware mode ..... ....................................................................................................... .27 10.1 channel status, user and validity data ......................................................................... 27 10.2 serial audio port formats .............................................................................................. 27 11. pin description - hardware mode ....................................................................... 29 12. applications ............................................................................................................. ....... 31 12.1 reset, power down and start-up .................................................................................. 31 12.2 id code and revision code .......................................................................................... 31 12.3 power supply, grounding, and pcb layout ................................................................... 31 12.4 synchronization of multiple cs8405as .......................................................................... 31 13. package dimensions .. ................................................................................................. 32
cs8405a ds469f2 3 14. appendix a: external aes3/spdif/iec60958 transmitter and receiver compo- nents ......................................................................................................................... ......... 34 14.1 aes3 transmitter external com ponents ....................................................................... 34 14.2 isolating transformer requirements ............................................................................. 34 15. appendix b: channel status and user data buffer management ........... 35 15.1 aes3 c hannel status(c) bit management .................................................................... 35 15.1.1 accessing the e buffer ...................................................................................... 35 15.1.2 serial copy management system (scms) ....................................................... 36 15.1.3 channel status data e buffer access .............................................................. 36 15.2 aes3 user (u) bit man agement .................................................................................... 36 15.2.1 mode 1: transmit all zeros ............................................................................... 36 15.2.2 mode 2: block mode ......................................................................................... 36 16. revision history ......................................................................................................... ... 37 list of figures figure 1. audio port master mode timing ...................................................................................... 7 figure 2. audio port slave mode and data input timing................................................................ 7 figure 3. spi mode timing...................................................................................................... ......... 8 figure 4. i2c mode timing...................................................................................................... .......... 9 figure 5. recommended connection diagram for software mode .............................................. 10 figure 6. serial audio input example formats ............................................................................. 12 figure 7. aes3 transmitter timing for c, u, and v pin input data .............................................. 14 figure 8. control port timing in spi mode ................................................................................... 15 figure 9. control port timing in i2c mode .................................................................................... 16 figure 10. hardware mode ....................................................................................................... .... 27 figure 11. professional output circuit ......................................................................................... .34 figure 12. consumer output circuit ............................................................................................. 34 figure 13. ttl/cmos output circuit............................................................................................ 3 4 figure 14. channel status data buffer structure.......................................................................... 35 figure 15. flowchart for writing the e buffer ................................................................................ 35 list of tables table 1. control register map summary...................................................................................... 17 table 2. hardware mode copy/c and orig pin functions ......................................................... 27 table 3. hardware mode serial audio port format selection ...................................................... 28 table 4. equivalent register settings of serial audio input formats available in hardware mode28 table 5. revision history ...................................................................................................... ........ 37
cs8405a 4 ds469f2 1. characteristics and specifications (all min/max characteristics and specifications are guarant eed over the specified operating conditions. typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and t a = 25c.) specified operating conditions (dgnd = 0 v, all voltages with respect to 0 v) notes: 1. i2c protocol is supported only in vl+ = 5.0 v mode. absolute maximum ratings (dgnd = 0 v; all voltages with respect to 0 v. operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes.) notes: 2. transient currents of up to 100 ma will not cause scr latch-up. parameter symbol min typ max units power supply voltage (note 1) vd+ vl+ 4.5 2.85 5.0 3.3 or 5.0 5.5 5.5 v v ambient operating temperature: ?-cs? & ?-cz? ?-is? & ?-iz? t a -10 -40 - - +70 +85 c parameter symbol min max units power supply voltage vd+,vl+ - 6.0 v input current, any pin except supplies (note 2) i in -10ma input voltage v in -0.3 (vl+) + 0.3 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c
cs8405a ds469f2 5 dc electrical characteristics (dgnd = 0 v; all voltages with respect to 0 v.) notes: 3. power down mode is defined as rst = lo with all clocks and data lines held static. 4. normal operation is defined as rst = hi. digital input characteristics digital interface specifications (dgnd = 0 v; all voltages with respect to 0 v.) notes: 5. at 5.0 v mode, v il = 0.8 v (max), at 3.3 v mode, v il =0.4 v (max). transmitter characteristics parameters symbol min typ max units power-down mode (note 3) supply current in power down vd+ vl+ = 3.3 v vl+ = 5.0 v - - - 20 60 60 - - - a a a normal operation (note 4) supply current at 48 khz frame rate vd+ vl+ = 3.3 v vl+ = 5.0 v - - - 6.3 30.1 46.5 - - - ma ma ma supply current at 96 khz frame rate vd+ vl+ = 3.3 v vl+ = 5.0 v - - - 6.6 44.8 76.6 - - - ma ma ma parameters symbol min typ max units input leakage current i in -110 a parameters symbol min max units high-level output voltage (i oh = -3.2 ma), except txp/txn v oh (vl+) - 1.0 - v low-level output voltage (i ol = 3.2 ma), except txp/txn v ol -0.4v high-level output voltage, txp, txn (23 ma at vl+ = 5.0 v) (15.2 ma at vl+ = 3.3 v) (vl+) - 0.7 (vl+) - 0.7 - - v v low-level output voltage, txp, txn (23 ma at vl+ = 5.0 v) (15.2 ma at vl+ = 3.3 v) - - 0.7 0.7 v v high-level input voltage v ih 2.0 (vl+) + 0.3 v low-level input voltage (note 5) v il -0.3 0.4/0.8 v parameters symbol min typ max units txp output resistance vl+ = 5.0 v vl+ = 3.3 v r txp - - 26 40 - - ? ? txn output resistance vl+ = 5.0 v vl+ = 3.3 v r txn - - 26 40 - - ? ?
cs8405a 6 ds469f2 switching characteristics (inputs: logic 0 = 0 v, logic 1 = vl+; c l = 20 pf) switching characteristics - serial audio ports (inputs: logic 0 = 0 v, logic 1 = vl+; c l = 20 pf) notes: 6. the active edge of isclk is programmable. 7. the polarity of ilrck is programmable. 8. no more than 128 sclk per frame. 9. prevents the previous isclk edge from being interpreted as the first one after ilrck has changed. 10. this setup time ensures that this isclk edge is interpreted as the first one after ilrck has changed parameter symbol min typ max units rst pin low pulse width 200 - - s omck frequency for omck = 512 * fso 4.1 - 55.3 mhz omck low and high width for omck = 512 * fso 7.2 - - ns omck frequency for omck = 384 * fso 3.1 - 41.5 mhz omck low and high width for omck = 384 * fso 10.8 - - ns omck frequency for omck = 256 * fso 2.0 - 27.7 mhz omck low and high width for omck = 256 * fso 14.4 - - ns frame rate 8.0 - 108.0 khz aes3 transmitter output jitter - - 1 ns parameter symbol min typ max units sdin setup time before isclk active edge (note 6) t ds 20 - - ns sdin hold time after isclk active edge (note 6) t dh 20 - - ns master mode omck to isclk active edge delay (note 6) t smd 0 - 10 ns omck to ilrck delay (note 7) t lmd 0 - 10 ns isclk and ilrck duty cycle - 50 - % slave mode isclk period (note 8) t sckw 36 - - ns isclk input low width t sckl 14 - - ns isclk input high width t sckh 14 - - ns isclk active edge to ilrck edge (note 6,7,9) t lrckd 20 - - ns ilrck edge setup before isclk active edge (note 6,7,10) t lrcks 20 - - ns
cs8405a ds469f2 7 isclk ilrck (output) (output) omck (input) t smd t lmd sckh sckl sckw t t t (input) (input) sdin dh t ds t lrcks t lrckd t isclk ilrck figure 1. audio port master mode timing figure 2. audio port slave mode and data input timing
cs8405a 8 ds469f2 switching characteristics - co ntrol port - spi mode (inputs: logic 0 = 0 v, logic 1 = vl+; c l = 20 pf) notes: 11. if fs is lower than 46.875 khz, the maximum cclk frequency should be less than 128 fs. this is dictated by the timing requirements necessary to access the channel status and user bit buffer memory. access to the control register file can be carried out at the full 6 mhz rate. the minimum allowable input sample rate is 8 khz, so choosing cclk to be less than or equal to 1.024 mhz should be safe for all possible conditions. 12. data must be held for sufficient time to bridge the transition time of cclk. 13. for f sck < 1 mhz. parameter symbol min typ max units cclk clock frequency (note 11) f sck 0-6.0mhz cs high time between transmissions t csh 1.0 - - s cs falling to cclk edge t css 20 - - ns cclk low time t scl 66 - - ns cclk high time t sch 66 - - ns cdin to cclk rising setup time t dsu 40 - - ns cclk rising to data hold time (note 12) t dh 15 - - ns cclk falling to cdout stable t pd - - 50 ns rise time of cdout t r1 - - 25 ns fall time of cdout t f1 - - 25 ns rise time of cclk and cdin (note 13) t r2 - - 100 ns fall time of cclk and cdin (note 13) t f2 - - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t pd cdout t csh figure 3. spi mode timing
cs8405a ds469f2 9 switching characteristics - control port - i2c mode (note 14, inputs: logic 0 = 0 v, logic 1 = vl+; c l = 20 pf) notes: 14. i2c protocol is supported only in vl+ = 5.0 v mode. 15. data must be held for sufficient time to bridge the 300 ns transition time of scl. parameter symbol min typ max units scl clock frequency f scl - - 100 khz bus free time between transmissions t buf 4.7 - - s start condition hold time (prior to first clock pulse) t hdst 4.0 - - s clock low time t low 4.7 - - s clock high time t high 4.0 - - s setup time for repeated start condition t sust 4.7 - - s sda hold time from scl falling (note 15) t hdd 0- - s sda setup time to scl rising t sud 250 - - ns rise time of both sda and scl lines t r - - 25 ns fall time of both sda and scl lines t f - - 25 ns setup time for stop condition t susp 4.7 - - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl figure 4. i2c mode timing
cs8405a 10 ds469f2 2. typical connection diagram 3-wire serial audio source ilrck isclk sdin clock source and control omck hardware control rst tcbl to other cs8405's cable interface aes3/ spdif equipment txp txn sda/cdout ad0/cs scl/cclk ad1/cdin u int vd+ vl+ 0.1 f h/s dgnd dgnd4 0.1 f ad2 rxp dgnd2 dgnd3 nc1 nc2 nc3 nc4 nc5 cs8405a +3.3 v or +5.0 v supply +5.0 v supply microcontroller aes3 data source figure 5. recommended connection diagram for software mode
cs8405a ds469f2 11 3. general description the cs8405a is a monolithic cmos device which encodes and transmits audio data according to the aes3, iec60958, s/pdif, and eiaj cp1201 inter- face standards. the cs8405a accepts audio, channel status and user data, which is then multi- plexed, encoded, and driven onto a cable. the audio data is input through a configurable, 3-wire input port. the channel status bits and user bit data are input through an spi or i2c mode mi- crocontroller port and may be assembled in sepa- rate block sized buffers. for systems with no microcontroller, a stand alone mode allows direct access to channel status and user data input pins. target applications include cd-r, dat, dvd, md and vtr equipment, mixing consoles, digital audio transmission equipment, high quality a/d convert- ers, effects processors, set-top tv boxes, and computer audio systems. figure 5 shows the supply and external connec- tions to the cs8405a when configured for opera- tion with a microcontroller. 3.1 aes3 and s/pdif standards documents this data sheet assumes that the user is familiar with the aes3 and s/pdif data formats. it is advis- able to have current copies of the aes3 and iec60958 specifications on hand for easy refer- ence. the latest aes3 standard is available from the au- dio engineering society or ansi at www.aes.org or www.ansi.org. obtain the latest iec60958 stan- dard from ansi or from the international electro- technical commission at www.iec.ch. the latest eiaj cp-1201 standard is available from the jap- anese electronics bureau. crystal application note 22: overview of digital audio interface data structures contains a useful tutorial on digital audio specifications, but it should not be considered a substitute for the standards. the paper an understanding and implementation of the scms serial copy management system for digital audio transmission , by clifton sanchez, is an excellent tutorial on scms. it is available from the aes as preprint 3518. 4.three-wire serial input audio port a 3-wire serial audio input port is provided. the in- terface format can be adjusted to suit the attached device through the control registers. the following parameters are adjustable: master or slave serial clock frequency audio data resolution left or right justification of the data relative to left/right clock optional one-bit cell delay of the first data bit polarity of the bit clock polarity of the left/right clock. (by setting the appropriate control bits, many formats are pos- sible). figure 6 shows a selection of common input for- mats with the corresponding control bit settings. in master mode, the left/right clock and the serial bit clock are outputs, derived from the omck input pin master clock. in slave mode, the left/right clock and the serial bit clock are inputs. the left/right clock must be syn- chronous to the omck master clock, but the serial bit clock can be asynchronous and discontinuous if required. the left/right clock should be continuous, but the duty cycle can be less than the specified typical value of 50% if enough serial clocks are present in each phase to clock all the data bits.
cs8405a 12 ds469f2 ilrck isclk sdin 2 left justified (in) msb lsb left right msb i s (in) right justified (in) msb lsb msb lsb msb left right msb lsb msb lsb left right lsb msb lsb ilrck isclk sdin ilrck isclk sdin figure 6. serial audio input example formats x = don?t care to match format, but does need to be set to the desired setting + i2s can accept an arbitrary number of bits, determined by the number of isclk cycles * see serial input port data format register bit descriptions for an explanation of the meaning of each bit sims* sisf* sires[1:0]* sijust* sidel* sispol* silrpol* left justified x x 00+ 0 0 0 0 i2s xx00+0 1 0 1 right justified x x xx 1 0 0 0
cs8405a ds469f2 13 5. aes3 transmitter the cs8405a includes an aes3 digital audio transmitter. a comprehensive buffering scheme provides write access to the channel status and user data. this buffering scheme is described in ?appendix b: channel status and user data buffer management? on page 35. the aes3 transmitter encodes and transmits au- dio and digital data according to the aes3, iec60958 (s/pdif), and eiaj cp-1201 interface standards. audio and control data are multiplexed together and bi-phase mark encoded. the result- ing bit stream is driven to an output connector ei- ther directly or through a transformer. the transmitter is clocked from the clock input pin, om-k. if omck is asynchronous to the data source, an interrupt bit (tslip) is provided that will go high every time a data sample is dropped or re- peated. be aware that the pattern of slips does not have hysteresis and so the occurrence of the inter- rupt condition is not deterministic. the channel status (c) and user (u) bits in the transmitted data stream are taken from storage ar- eas within the cs8405a. the user can manually access the internal storage or configure the cs8405a to run in one of several automatic modes. ?appendix b: channel status and user data buffer management? on page 35 provides de- tailed descriptions of each automatic mode and de- scribes methods of manually accessing the storage areas. the transmitted user bit data can optionally be input through the u pin, under the control of a control port register bit. figure 7 shows the timing requirements for inputting u data through the u pin. 5.1 transmitted frame and channel status boundary timing the tcbl pin is used to control or indicate the start of transmitted channel status block boundaries and may be an input or an output. in some applications, it may be necessary to con- trol the precise timing of the transmitted aes3 frame boundaries. this may be achieved in two ways: a) with tcbl set to input, driving tcbl high for >3 omck clocks will cause a frame start, as well as a new channel status block start. b) if the serial audio input port is in slave mode and tcbl is set to output, the start of the a channel sub-frame will be aligned with the leading edge of ilrck. 5.2 txn and txp drivers the line drivers are low skew, low impedance, dif- ferential outputs capable of driving cables directly. both drivers are set to ground during reset (rst = low), when no aes3 transmit clock is provided, and optionally under the control of a register bit. the cs8405a also allows immediate muting of the aes3 transmitter audio data through a control reg- ister bit. external components are used to terminate and isolate the external cable from the cs8405a. these components are detailed in ?appendix a: external aes3/spdif/iec60958 transmitter and receiver components? on page 34. 5.3 mono mode operation an aes3 stream may be used in more than one way to transmit 96 khz sample rate data. one method is to double the frame rate of the current format. this results in a stereo signal with a sample rate of 96 khz, carried over a single twisted pair cable. an alternate method is implemented using the two sub-frames in a 48 khz frame rate aes3 signal to carry consecutive samples of a mono sig- nal, resulting in a 96 khz sample rate stream. this allows older equipment, whose aes3 transmitters and receivers are not rated for 96 khz frame rate operation, to handle 96 khz sample rate informa- tion. in this ?mono mode?, two aes3 cables are needed for stereo data transfer. the cs8405a of- fers mono mode operation. the cs8405a is set to mono mode by the mmt control bit. in mono mode, the input port will run at the audio sample rate (fs), while the aes3 transmitter frame rate will be at fs/2. consecutive left or right chan- nel serial audio data samples may be selected for transmission on the a and b sub-frames, and the channel status block transmitted is also selectable. using mono mode is only necessary if the incom- ing audio sample rate is already at 96 khz and contains both left and right audio data words. the ?mono mode? aes3 output stream may also be achieved by keeping the cs8405a in normal
cs8405a 14 ds469f2 stereo mode, and placing consecutive audio sam- ples in the left and right positions in an incoming 48 khz word rate data stream. vcu[0] vcu[1] vcu[2] vcu[3] vcu[4] tcbl in or out vlrck vcu input data [4] data [5] data [6] data [7] data [8] sdin input data [0] data [1] data [2] data [3] data [4] txp(n) output z y x y x aes3 transmitter in stereo mode u[0] u[2] tcbl in or out vlrck u input data [4] data [5] data [6] data [7] data [8] sdin input data [0]* data [2]* data [4]* txp(n) output z y x * assume mmtlr = 0 tsetup => 7.5% aes3 frame time thold = 0 tsetup thold data [1]* data [3]* data [5]* txp(n) output zy x aes3 transmitter in mono mode * assume mmtlr = 1 tsetup => 15% aes3 frame time thold = 0 vlrck is a virtual word clock, which may not exist, and is used to illustrate the cuv timing. vlrck duty cycle is 50%. in stereo mode, vlrck frequency = aes3 frame rate. in mono mode, alrck frequency = 2xaes3 frame rate . if the serial audio input port is on slave mode and tcbl is an output, then vlrck=ilrck if silrpol=0 and vlrck= ilrck if silrpol =1. if the serial audio input port is in master mode and tcbl is an input, then vlrck=ilrck if silrpol=0 and vlrck= ilrck if silrpol =1. tth tth > 3omck if tcbl is input tth > 3omck if tcbl is input tth figure 7. aes3 transmitter timing for c, u, and v pin input data
cs8405a ds469f2 15 6. control port description and timing the control port is used to access the registers, al- lowing the cs8405a to be configured for the de- sired operational modes and formats. in addition, channel status and user data may be read and written through the control port. the operation of the control port may be completely asynchronous with respect to the audio sample rate. the control port has two modes: spi and i2c, with the cs8405a acting as a slave device. spi mode is selected if there is a high to low transition on the ad0/cs pin after the rst pin has been brought high. i2c mode is selected by connecting the ad0/cs pin to vl+ or dgnd, thereby permanently selecting the desired ad0 bit address state. 6.1 spi mode in spi mode, cs is the cs8405a chip select sig- nal, cclk is the control port bit clock (input into the cs8405a from the microcontroller); cdin is the in- put data line from the microcontroller; and cdout is the output data line to the microcontroller. data is clocked in on the rising edge of cclk and out on the falling edge. figure 8 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and must be 0010000. the eighth bit is a read/write in- dicator (r/w ), which should be low to write. the next eight bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next eight bits are the data which will be placed into the register designat- ed by the map. during writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k ? resistor, if desired. there is a map auto increment capability, enabled by the incr bit in the map register. if incr is a zero, the map will stay constant for successive read or writes. if incr is set to a 1, then the map will auto increment after each byte is read or written, allowing block reads or writes of successive registers. to read a register, the map has to be set to the correct address by executing a partial write cycle which finishes (cs high) immediately after the map byte. the map auto increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high impedance state). if the map auto increment bit is set to 1, the data for successive registers will appear consecutively. 6.2 i2c mode in i2c mode, sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with the clock to data relationship as shown in figure 9. there is no cs pin. each individual cs8405a is given a unique address. pins ad0, ad1, and ad2 form the three least significant bits map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 0010000 0010000 map = memory address pointer, 8 bits, msb first high impedance figure 8. control port timing in spi mode
cs8405a 16 ds469f2 of the chip address, and should be connected to vl+ or dgnd as desired. the upper four bits of the seven-bit address field are fixed at 0010. to com- municate with a cs8405a, the chip address field, which is the first byte sent to the cs8405a, should match 0010 followed by the settings of ad2, ad1, and ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map) which selects the register to be read or written. if the operation is a read, the contents of the register pointed to by the map will be output. setting the auto increment bit in map allows successive reads or writes of con- secutive registers. each byte is separated by an acknowledge bit, ack, which is output from the cs8405a after each input byte is read. the ack bit is input to the cs8405a from the microcontroller after each transmitted byte. i2c mode is supported only with vl+ = 5.0 v. 6.3 interrupts the cs8405a has a comprehensive interrupt ca- pability. the int output pin is intended to drive the interrupt input pin on the host microcontroller. the int pin may be set to be active low, active high or active low with no active pull-up transistor. this last mode is used for active low, wired-or hook-ups, with multiple peripherals connected to the micro- controller interrupt input pin. many conditions can cause an interrupt, as listed in the interrupt status register descriptions. each source may be masked off by a bit in the mask reg- isters. in addition, each source may be set to rising edge, falling edge, or level sensitive. combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different set-ups are possible, depending on the needs of the equipment designer. sda scl 0010 ad2-0 r/w start ack data7-0 ack data7-0 ack stop note 2 note 1 note 3 figure 9. control port timing in i2c mode notes: 1. ad2, ad1, and ad0 are determined by the state of the corresponding pins. 2. if operation is a write, this byte contains the memory address pointer, map. 3. if operation is a read, the last bit of the read should be nack (high).
cs8405a ds469f2 17 7. control port register summary 7.1 memory address pointer (map) incr - auto increment address control bit default = ?0? 0 - disable 1 - enable map6:map0 - register address note: reserved registers must not be written to during normal operation. some reserved registers are used for test modes, which can completely alter the normal operation of the cs8405a. addr (hex) function 7 6 5 4 3 2 1 0 00 reserved 0 0 0 0 0 0 0 0 01 control 1 0 vset 0 muteaes 0 int1 int0 tcbld 02 control 2 0 0 0 0 0 mmt mmcst mmtlr 03 data flow control 0 txoff aesbp 0 0 0 0 0 04 clock source control 0 run clk1 clk0 0 0 0 0 05 serial input format sims sisf sires1 sires0 sijust sidel sispol silrpol 06 reserved 0 0 0 0 0 0 0 0 07 interrupt 1 status tslip 0 0 0 0 0 eftc 0 08 interrupt 2 status 0 0 0 0 0 eftu 0 0 09 interrupt 1 mask tslipm 0 0 0 0 0 eftcm 0 0a interrupt 1 mode (msb) tslip1 0 0 0 0 0 eftc1 0 0b interrupt 1 mode (lsb) tslip0 0 0 0 0 0 eftc0 0 0c interrupt 2 mask 0 0 0 0 0 eftum 0 0 0d interrupt 2 mode (msb) 0 0 0 0 0 eftu1 0 0 0e interrupt 2 mode (lsb) 0 0 0 0 0 eftu0 0 0 0f-11 reserved 0 0 0 0 0 0 0 0 12 cs data buffer control 0 0 bsel 0 0 eftci cam 0 13 u data buffer control 0 0 0 ud ubm1 ubm0 0 eftui 14-1f reserved 0 0 0 0 0 0 0 0 20-37 c or u data buffer 7f id and version id3 id2 id1 id0 ver3 ver2 ver1 ver0 table 1. control register map summary 7 6 543210 incr map6 map5 map4 map3 map2 map1 map0
cs8405a 18 ds469f2 8. control port register bit definitions 8.1 control 1 (01h) vset - transmitted validity bit level default = ?0? 0 - indicates data is valid, linear pcm audio data 1 - indicates data is invalid or not linear pcm audio data muteaes - mute control for the aes transmitter output default = ?0? 0 - not muted 1 - muted int1:0 - interrupt output pin (int) control default = ?00? 00 - active high; high output indicates interrupt condition has occurred 01 - active low, low output indicates an interrupt condition has occurred 10 - open drain, active low. requires an external pull-up resistor on the int pin. 11 - reserved tcbld - transmit channel status block pin (tcbl) direction specifier default = ?0? 0 - tcbl is an input 1 - tcbl is an output 8.2 control 2 (02h) mmt - select aes3 transmitter mono or stereo operation default = ?0? 0 - normal stereo operation 1 - output either left or right channel inputs into consecutive subframe outputs (mono mode, left or right is determined by mmtlr bit) mmtcs - select a or b channel status data to transmit in mono mode default = ?0? 0 - use channel a cs data for the a subframe and use channel b cs data for the b subframe 1 - use the same cs data for both the a and b subframe outputs. if mmtlr = 0, use the left channel cs data. if mmtlr = 1, use the right channel cs data. 7 6 543210 0 vset 0 muteaes 0 int1 int0 tcbld 7 6 543210 0 0 0 0 0 mmt mmtcs mmtlr
cs8405a ds469f2 19 mmtlr - channel selection for aes transmitter mono mode default = ?0? 0 - use left channel input data for consecutive subframe outputs 1- use right channel input data for consecutive subframe outputs 8.3 data flow control (03h) the data flow control register configures the flow of audio data. the output data should be muted prior to changing bits in this register to avoid transients. txoff - aes3 transmitter output driver control default = ?0 0 - aes3 tr ansmitter output pin dr ivers normal operation 1 - aes3 transmitter output pin drivers drive to 0 v. aesbp - aes3 bypass mode selection default = ?0? 0 - normal operation 1 - connect the aes3 transmitter driver input directly to the rxp pin, which becomes a normal ttl threshold digital input. the omck clock must be present for the bypass mode to work. 8.4 clock source control (04h) this register configures the clock sources of various blocks. in conjunction with the data flow control register, various receiver/transmitter/transceiver modes may be selected. run - controls the internal clocks, allowing the cs8405a to be placed in a ?powered down? low current consumption, state. default = ?0? 0 - internal clocks are stopped. internal state machines are reset. the fully static control port registers are operational, allowing registers to be read or changed. reading and writing the u and c data buffers is not possible. power consumption is low. 1 - normal part operation. this bit must be set to 1 to allow the cs8405a to begin operation. all input clocks should be stable in frequency and phase when run is set to 1. clk1:0 - output master clock (omck) input frequency to output sample rate (fs) ratio selector. if these bits are changed during normal operation, then always stop the cs8405a first (run = 0), write the new value, then start the cs8405a (run = 1). default = ?00? 00 - omck frequency is 256*fs 01 - omck frequency is 384*fs 10 - omck frequency is 512*fs 11 - reserved 7 6 543210 0txoffaesbp00000 7 6 543210 0runclk1clk00000
cs8405a 20 ds469f2 8.5 serial audio input port data format (05h) sims - master/slave mode selector default = ?0? 0 - serial audio input port is in slave mode 1 - serial audio input port is in master mode sisf - isclk frequency (for master mode) default = ?0? 0 - 64*fs 1 - 128*fs sires1:0 - resolution of the input data, for right-justified formats default = ?00? 00 - 24-bit resolution 01 - 20-bit resolution 10 - 16-bit resolution 11 - reserved sijust - justification of sdin data relative to ilrck default = ?0? 0 - left-justified 1 - right-justified sidel - delay of sdin data relative to ilrck, for left-justified data formats default = ?0? 0 - msb of sdin data occurs in the first isclk period after the ilrck edge (left justified mode) 1 - msb of sdin data occurs in the second isclk period after the ilrck edge (i2s mode) sispol - isclk clock polarity default = ?0? 0 - sdin sampled on rising edges of isclk 1 - sdin sampled on falling edges of isclk silrpol - ilrck clock polarity default = ?0? 0 - sdin data is for the left channel when ilrck is high 1 - sdin data is for the right channel when ilrck is high 7 6 543210 sims sisf sires1 sires0 sijust sidel sispol silrpol
cs8405a ds469f2 21 8.6 interrupt 1 status (07h) (read only) for all bits in this register, a ?1? means the associated interrupt condition has occurred at least once since the register was last read. a ?0? means the associated interrupt condition has not occurred since the last reading of the register. reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. status bits that are masked off in the associated mask register will always be ?0? in this register. this register defaults to 00h. tslip - aes3 transmitter source data slip interrupt in data flows where omck, which clocks the aes3 transmitter, is asynchronous to the data source, this bit will go high every time a data sample is dropped or repeated. when tcbl is an input, this bit will go high on receipt of a new tcbl signal. eftc - e to f c-buffer transfer interrupt. the source for this bit is true during the e to f buffer transfer in the c bit buffer management process. 8.7 interrupt 2 status (08h) (read only) for all bits in this register, a ?1? means the associated interrupt condition has occurred at least once since the register was last read. a ?0? means the associated interrupt condition has not occurred since the last reading of the register. reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. status bits that are masked off in the associated mask register will always be ?0? in this register. this register defaults to 00h. eftu - e to f u-buffer transfer interrupt. (block mode only) the source of this bit is true during the e to f buffer transfer in the u bit buffer management process. 8.8 interrupt 1 mask (09h) the bits of this register serve as a mask for the interrupt 1 register. if a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the int pin and the status register. if a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the int pin or the status register. the bit positions align with the corresponding bits in interrupt 1 register. this register defaults to 00h. 7 6 543210 tslip0 0000eftc0 7 6 543210 00000eftu00 7 6 543210 tslipm0 0000eftcm0
cs8405a 22 ds469f2 8.9 interrupt 1 mode msb (0ah) and interrupt 1 mode lsb (0bh) the two interrupt mode registers form a 2-bit code for each interrupt register 1 function. there are three ways to set the int pin active in accordance with the interrupt condition. in the rising edge ac- tive mode, the int pin becomes active on the arrival of the interrupt condition. in the falling edge ac- tive mode, the int pin becomes active on the removal of the interrupt condition. in level active mode, the int interrupt pin becomes active during the interrupt condition. be aware that the active level (ac- tice high or low) only depends on the int[1:0] bits. these registers default to 00. 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 8.10 interrupt 2 mask (0ch) the bits of this register serve as a mask for the interrupt 2 register. if a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the int pin and the status register. if a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the int pin or the status register. the bit positions align with the corresponding bits in interrupt 2 register. this register defaults to 00h. 8.11 interrupt 2 mode msb (0dh) and interrupt mode 2 lsb (0eh) the two interrupt mode registers form a 2-bit code for each interrupt register 1 function. there are three ways to set the int pin active in accordance with the interrupt condition. in the rising edge ac- tive mode, the int pin becomes active on the arrival of the interrupt condition. in the falling edge ac- tive mode, the int pin becomes active on the removal of the interrupt condition. in level active mode, the int interrupt pin becomes active during the interrupt condition. be aware that the active level (ac- tive high or low) only depends on the int[1:0] bits. these registers default to 00. 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 7 6 543210 tslip1 0 0 0 0 0 eftc1 0 tslip0 0 0 0 0 0 eftc0 0 7 6 543210 00000eftum00 7 6 543210 0 0 0 0 0 eftu1 0 0 0 0 0 0 0 eftu0 0 0
cs8405a ds469f2 23 8.12 channel status data buffer control (12h) bsel - selects the data buffer register addresses to contain user data or channel status data default = ?0? 0 - data buffer address space contains channel status data 1 - data buffer address space contains user data note: there are separate complete buffers for the channel status and user bits. this control bit determines which buffer appears in the address space. eftci - e to f c-data buffer transfer inhibit bit. default = ?0? 0 - allow c-data e to f buffer transfers 1 - inhibit c-data e to f buffer transfers cam - c-data buffer control port access mode bit default = ?0? 0 - one byte mode 1 - two byte mode 8.13 user data buffer control (13h) ud - user bit data source specifier default = ?0? 0 - the u pin is an input. the user bit data is latched in on both rising and falling edges of olrck. this setting also chooses the u pin as the source for transmitted u data. 1 - sets the u data buffer as the source of transmitted u data. the u pin also becomes an indeterminate output. ubm1:0 - sets the operating mode of the aes3 user bit manager default = ?00? 00 - transmit all zeros mode 01 - block mode 10 - reserved 11 - reserved eftui - e to f u-data buffer transfer inhibit bit (valid in block mode only). default = ?0? 0 - allow u-data e to f buffer transfers 1 - inhibit u-data e to f buffer transfer 7 6 543210 0 0 bsel 0 0 eftci cam 0 7 6 543210 0 0 0 ud ubm1 ubm0 0 eftui
cs8405a 24 ds469f2 8.14 channel status bit or user bit data buffer (20h - 37h) either the channel status data buffer e or the separate user bit data buffer e (provided ubm bits are set to block mode) is accessible through these register addresses. 8.15 cs8405a i.d. and version register (7fh) (read only) id3:0 - id code for the cs8405a. permanently set to 0110 ver3:0 - cs8405a revision level. revision a is coded as 0001 7 6 543210 id3 id2 id1 id0 ver3 ver2 ver1 ver0
cs8405a ds469f2 25 9. pin description - software mode sda / cdout scl / cclk ad0 / cs ad1 / cdin ad2 txp rxp txn dgnd2 h/s vd+ vl+ dgnd4 dgnd dgnd3 omck rst u nc1 int nc2 nc5 ilrck nc4 isclk nc3 sdin tcbl 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16 vd+ 6 digital power ( input ) - digital core power supply. typically +5.0 v. vl+ 23 logic power ( input ) - input/output power supply. typically +3.3 v or +5.0 v. dgnd dgnd2 dgnd3 dgnd4 22 5 8 7 ground ( input ) - ground for i/o and core logic. rst 9 reset ( input ) - when rst is low, the cs8405a enters a low power mode and all internal states are reset. on initial power up, rst must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. this is particularly true in hardware mode with multiple cs8405a devices, where synchronization between devices is important. h/s 24 hardware/software control mode select ( input ) -determines the method of controlling the operation of the cs8405a, and the method of accessing channel status and user bit data. in software mode, device control and cs and u data access is primarily through the control port, using a microcontroller. hardware mode provides an alternate mode of operation, and access to cs and u data is provided by dedicated pins. this pin should be permanently tied to vl+ or dgnd. txn txp 25 26 differential line drivers ( output ) - these pins transmit biphase encoded data. the drivers are pulled low while the cs8405a is in the reset state. omck 21 master clock ( input ) - the frequency must be 256x, 384x, or 512x the sample rate.
cs8405a 26 ds469f2 isclk 13 serial audio bit clock ( input / output ) - serial bit clock for audio data on the sdin pin. ilrck 12 serial audio input left/right clock ( input / output ) - word rate clock for the audio data on the sdin pin. sdin 14 serial audio data port ( input ) - audio data serial input pin. sda/cdou t 1 serial control data i/o (i2c mode) / data out (spi) ( input/output ) - in i2c mode, sda is the control i/o data line. sda is open drain and requires an external pull-up resistor to vl+. in spi mode, cdout is the output data from the control port interface on the cs8405a scl/cclk 28 control port clock ( input ) - serial control interface clock and is used to clock control data bits into and out of the cs8405a. in i2c mode, scl requires an external pull-up resistor to vl+. ad0/cs 2 address bit 0 (i2c mode) / control port chip select (spi) ( input) - a falling edge on this pin puts the cs8405a into spi control port mode. with no falling edge, the cs8405a defaults to i2c mode. in i2c mode, ad0 is a chip address pin. in spi mode, cs is used to enable the con- trol port interface on the cs8405a ad1/cdin 27 address bit 1 (i2c mode) / serial control data in (spi) ( input ) - in i2c mode, ad1 is a chip address pin. in spi mode, cdin is the input data line for the control port interface. ad2 3 address bit 2 (i2c mode) ( input ) - determines the ad2 address bit for the control port in i2c mode, and should be connected to dgnd or vl+. if spi mode is used, the ad2 pin should be connected to dgnd. rxp 4 auxiliary aes3 receiver port ( input ) - input for an alternate, already bi-phase encoded, audio data source. int 19 interrupt ( output ) - indicates key events during the operation of the cs8405a. all bits affect- ing int may be unmasked through bits in the control registers. indication of the condition(s) that initiated an interrupt are readable in the control registers. the polarity of the int output, as well as selection of a standard or open drain output, is set through a control register. once set true, the int pin goes false only after the interrupt status registers have been read and the interrupt status bits have returned to zero. tcbl 15 transmit channel status block start ( input / output ) - when operated as output, tcbl is high during the first sub-frame of a transmitted channel status block, and low at all other times. when operated as input, driving tcbl high for at least three omck clocks will cause the next transmitted sub-frame to be the start of a channel status block. u 20 user data ( input / output ) - may optionally be used to input user data for transmission by the aes3 transmitter, see figure 7 for timing information. alternatively, the u pin may be set to output, which also selects the internal buffer as the source of transmitted u data. if not driven, a 47 kw pull-down resistor is recommended for the u pin, because the default state of the ud direction bit sets the u pin as an input. the pull-down resistor ensures that the transmitted user data will be zero. if the u pin is always set to be an output, thereby causing the u bit manager to be the source of the u data, then the resistor is not necessary. the u pin should not be tied directly to ground, in case it is programmed to be an output, and subsequently tries to output a logic high. this situation may affect the long term reliability of the device. if the u pin is driven by a logic level output, then a 100 w series resistor is recommended. nc1 nc2 nc3 nc4 nc5 10 11 16 17 18 no connect - these pins should not be connected to any signals or pcb trace. they may be driven high and/or low by the cs8405a.
cs8405a ds469f2 27 10. hardware mode the cs8405a has a hardware mode that allows the use of the device without a microcontroller. hardware mode is selected by connecting the h/s pin to vl+. the flexibility of the cs8405a is neces- sarily limited in hardware mode. various pins change function as described in the hardware mode pin description section. the hardware mode data flow is shown in figure 10. audio data is input through the serial audio input port and routed to the aes3 transmit- ter. 10.1 channel status, user and validity data the transmitted channel status, user and validity data can be input in two methods, determined by the state of the cen pin. mode a is selected when the cen pin is low. in mode a, the user bit data and the validity bit are input through the u and v pins, clocked by both edges of ilrck. the channel sta- tus data is derived from the state of the copy/c, orig, emph , and audio pins. table 2 shows how the copy/c and orig pins map to channel status bits. in consumer mode, the transmitted cat- egory code is set to sample rate converter (0101100). mode b is selected when the cen pin is high. in mode b, the channel status, user data bits and the validity bit are input serially through the copy/c, u and v pins. data is clocked into these pins at both edges of ilrck. figure 7 shows the timing requirements. the channel status block pin (tcbl) may be an in- put or an output, determined by the state of the tcbld pin. 10.2 serial audio port formats the serial audio input port data format is selected as shown in table 3, and may be set to master or slave by the state of the apms input pin. table 4 describes the equivalent software mode, bit settings for each of the available formats. timing diagrams are shown in figure 6. aes3 encoder &tx serial audio input c, u, v data buffer ilrck isclk txp copy/c orig emph audio tcbl vl+ h/s output clock source omck power supply pins and the reset pin are omitted from this diagram. please refer to the typical connection diagram for hook-up details. sdin sfmt1 sfmt0 txn cen u v tcbld apms figure 10. hardware mode copy/c orig function 00 pro=0, copy=0, l=0 copyright 01 pro=0, copy=0, l=1 copyright, pre-recorded 10 pro=0, copy=1, l=0 non-copyright 11 pro=1 table 2. hardware mode copy/c and orig pin functions
cs8405a 28 ds469f2 sfmt1 sfmt0 function 00 serial input format if1 - left justified 01 serial input format if2 - i2s 10 serial input format if3 - right justified, 24-bit data 11 serial input format if4 - right justified, 16-bit data table 3. hardware mode serial audio port format selection sisf sires1/0 sijust sidel sispol silrpol if1 - left justified 0 00 0 0 0 0 if2 - i2s 0 00 0 1 0 1 if3 - right justified, 24-bit data 0 00 1 0 0 0 if4 - right justified, 16-bit data 0 10 1 0 0 0 table 4. equivalent register settings of serial audio input formats available in hardware mode
cs8405a ds469f2 29 11.pin description - hardware mode copy / c orig vl2+ vl4+ emph txp sfmt0 txn sfmt1 h/s vd+ vl+ dgnd4 dgnd dgnd3 omck rst vl3+ apms audio tcbld u ilrck v isclk cen sdin tcbl 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16 vd+ 6 digital power ( input ) - digital core power supply. typically +5.0 v. vl+ vl2+ vl3+ vl4+ 23 2 20 27 logic power ( input ) - input/output power supply. typically +3.3 v or +5.0 v. all vl+ pins must be at the same voltage. dgnd dgnd3 dgnd4 22 8 7 digital ground ( input ) - ground for the digital section. rst 9 reset ( input ) - when rst is low, the cs8405a enters a low power mode and all internal states are reset. on initial power up, rst must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. this is particularly true in hardware mode with multiple cs8405a devices, where synchronization between devices is important. h/s 24 hardware/software control mode select ( input ) -determines the method of controlling the opera- tion of the cs8405a, and the method of accessing cs and u data. in software mode, device control and cs and u data access is primarily through the control port, using a microcontroller. hardware mode provides an alternate mode of operation, and access to cs and u data is provided by dedi- cated pins. this pin should be permanently tied to vl+ or dgnd. txn txp 25 26 differential line drivers ( output ) - these pins transmit biphase encoded data. the drivers are pulled low while the cs8405a is in the reset state.
cs8405a 30 ds469f2 omck 21 master clock ( input ) - the frequency must be only 256x the sample rate. isclk 13 serial audio bit clock ( input / output ) - serial bit clock for audio data on the sdin pin. ilrck 12 serial audio input left/right clock ( input / output ) - word rate clock for the audio data on the sdin pin. sdin 14 serial audio data port ( input ) - audio data serial input pin. sfmt0 sfmt1 4 5 serial audio data format select ( input ) - selecta the serial audio input port format. see table 3. apms 10 serial audio data port master/slave select ( input ) - apms should be connected to vl+ to set serial audio input port as a master or connected to dgnd to set the port as a slave. tcbld 11 transmit channel status block direction ( input ) - connect tcbld to vl+ to set tcbl as an out- put. connect tcbld to dgnd to set tcbl as an input. tcbl 15 transmit channel status block start ( input / output ) - when operated as output, tcbl is high dur- ing the first sub-frame of a transmitted channel status block, and low at all other times. when oper- ated as input, driving tcbl high for at least three omck clocks will cause the next transmitted sub- frame to be the start of a channel status block. cen 16 c bit enable ( input ) - determines how the channel status data bits are input. when cen is low, hardware mode a is selected, where the copy/c, orig, emph and audio pins are used to enter selected channel status data. when cen is high, hardware mode b is selected, where the copy/c pin is used to enter serial channel status data. v 17 validity bit ( input ) - in hardware modes a and b, the v pin input determines the state of the validity bit in the outgoing aes3 transmitted data. this pin is sampled on both edges of the ilrck. u 18 user data bit ( input ) - in hardware modes a and b, the u pin input determines the state of the user data bit in the outgoing aes3 transmitted data. this pin is sampled on both edges of the ilrck. copy/c 1 copy channel status bit/c bit (input) - in hardware mode a (cen = 0), the copy/c and orig pins determine the state of the copyright, pro, and l channel status bits in the outgoing aes3 data stream, see table 2. in hardware mode b, the copy/c pin becomes the direct c bit input data pin. emph 3 pre-emphasis indicator ( input ) - in hardware mode a (cen = 0), the emph pin low sets the 3 emphasis channel status bits to indicate 50/15 ms pre-emphasis of the transmitted audio data. if emph is high, then the three emph channel status bits are set to 000, indicating no pre-emphasis. audio 19 audio channel status bit ( input ) - in hardware mode a (cen = 0), the audio pin determines the state of the audio/non audio channel status bit in the outgoing aes3 data stream. orig 28 orig channel status bit control ( input ) - in hardware mode a (cen = 0), the orig and copy/c pins determine the state of the copyright, pro, and l channel status bits in the outgoing aes3 data stream, see table 2.
cs8405a ds469f2 31 12. applications 12.1 reset, power down and start-up when rst is low, the cs8405a enters a low pow- er mode and all internal states are reset, including the control port and registers, and the outputs are disabled. when rst is high, the control port be- comes operational and the desired settings should be loaded into the control registers. writing a 1 to the run bit w ill then cause the part to leave the low power state and begin operation. 12.2 id code and revision code the cs8405a has a register that contains a four- bit code to indicate that the addressed device is a cs8405a. this is useful when other cs84xx fam- ily members are resident in the same or similar systems, allowing common software modules. the cs8405a four-bit revision level code is also available. this allows the software driver for the cs8405a to identify which revision of the device is in a particular system, and modify its behavior ac- cordingly. to allow for future revisions, it is strongly recommended that the revision code is read into a variable area within the microcontroller, and used wherever appropriate as revision details become known. 12.3 power supply, grounding, and pcb layout for most applications, the cs8405 can be operat- ed from a single +5.0 v supply, following normal supply decoupling practices, see figure 5. ?rec- ommended connection diagram for software mode? on page 10. note that the i2c protocol is supported only in vl+ = 5.0 v mode. the vl+ sup- plies should be decoupled with a 0.1 f capacitor to dgnd to minimize aes3 transmitter induced transients. extensive use of power and ground planes, ground plane fill in unused areas and surface mount de- coupling capacitors are recommended. decou- pling capacitors should be mounted on the same side of the board as the cs8405a to minimize in- ductance effects, and all decoupling capacitors should be as close to the cs8405a as possible. 12.4 synchronization of multiple cs8405as the aes3 transmitters of multiple cs8405as can be synchronized if all devices share the same mas- ter clock, tcbl, and rst signals and all exit the reset state on the same master clock falling edge. the tcbl pin is used to synchronize multiple cs8405a aes3 transmitters at the channel status block boundaries. one cs8405a must have its tcbl set to master; the others must be set to slave tcbl. alternatively, tcbl can be derived from ex- ternal logic, whereby all cs8405a devices should be set to slave tcbl.
cs8405a 32 ds469f2 13. package dimensions inches millimeters dim min nom max min nom max a 0.093 0.098 0.104 2.35 2.50 2.65 a1 0.004 0.008 0.012 0.10 0.20 0.30 b 0.013 0.017 0.020 0.33 0.42 0.51 c 0.009 0.011 0.013 0.23 0.28 0.32 d 0.697 0.705 0.713 17.70 17.90 18.10 e 0.291 0.295 0.299 7.40 7.50 7.60 e 0.040 0.050 0.060 1.02 1.27 1.52 h 0.394 0.407 0.419 10.00 10.34 10.65 l 0.016 0.026 0.050 0.40 0.65 1.27 0 4 8 0 4 8 jedec #: ms-013 controlling dimension is millimeters 28l soic (300 mil body) package drawing d h e b a1 a c l seating plane 1 e
cs8405a ds469f2 33 notes: 1.?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2.dimension ?b? does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3.these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a----0.47----1.20 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.03150 0.035 0.04 0.80 0.90 1.00 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.378 bsc 0.382 bsc 0.386 bsc 9.60 bsc 9.70 bsc 9.80 bsc 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.029 0.50 0.60 0.75 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 28l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs8405a 34 ds469f2 14. appendix a: external aes3/spdif/iec60958 transmitter and receiver components this section details the external components re- quired to interface the aes3 transmitter and re- ceiver to cables and fiber-optic components. 14.1 aes3 transmitter external components the output drivers on the cs8405a are designed to drive both the professional and consumer inter- faces. the aes3 specification for profession- al/broadcast use calls for a 110 ? source impedance and a balanced drive capability. since the transmitter output impedance is very low, a 110 ? resistor should be placed in series with one of the transmit pins. the specifications call for a balanced output drive of 2-7 v peak-to-peak into a 110 ? load with no cable attached. using the cir- cuit in figure 11 , the output of the transformer is short-circuit protected, has the proper source im- pedance, and provides a 5 v peak-to-peak signal into a 110 ? load. lastly, the two output pins should be attached to an xlr connector with male pins and a female shell, and with pin 1 of the con- nector grounded. in the case of consumer use, the iec60958 speci- fications call for an unbalanced drive circuit with an output impedance of 75 ? and a output drive level of 0.5 v peak-to-peak 20% when measured across a 75 ? load using no cable. the circuit shown in figure 12 only uses the txp pin and pro- vides the proper output impedance and drive level using standard 1% resistors. if vl+ is driven from +3.3 v, use resistor values of 243 ? and 107 ? . the connector for a consumer application would be an rca phono socket. this circuit is also short circuit protected. the txp pin may be used to drive ttl or cmos gates as shown in figure 13. this circuit may be used for optical connectors for digital audio since they usually have ttl or cmos compatible inputs. this circuit is also useful when driving multiple dig- ital audio outputs since rs422 line drivers have ttl compatible inputs. 14.2 isolating transformer requirements please refer to the application note an134: aes and spdif recommended transformers for re- sources on transformer selection. 110-(r txp +r txn ) txp txn xlr 1 cs8405a figure 11. professional output circuit figure 12. consumer output circuit 374-r txp 90.9 ? txp txn cs8405a figure 13. ttl/cmos output circuit txp txn ttl or cmos gate cs8405a
cs8405a ds469f2 35 15. appendix b: channel status and user data buffer management the cs8405a has a comprehensive channel sta- tus (c) and user (u) data buffering scheme which allows the user to manage the c and u data through the control port. 15.1 aes3 channel status(c) bit management the cs8405a contains sufficient ram to store a full block of c data for both a and b channels (192x2 = 384 bits), and also 384 bits of u informa- tion. the user may read from or write to these ram buffers through the control port. the cs8405a manages the flow of channel status data at the block level, meaning that entire blocks of channel status information are buffered at the in- put, synchronized to the output timebase, and then transmitted. the buffering scheme involves a cas- cade of 2 block-sized buffers, named e and f, as shown in figure 14. the msb of each byte repre- sents the first bit in the serial c data stream. for example, the msb of byte 0 (which is at control port address 20h) is the consumer/professional bit for channel status block a. the e buffer is accessible from the control port, al- lowing read and writing of the c data. the f buffer is used as the source of c data for the aes3 trans- mitter. the f buffer accepts block transfers from the e buffer. 15.1.1 accessing the e buffer the user can monitor the data being transferred by reading the e buffer, which is mapped into the reg- ister space of the cs8405a, through the control port. the user can modify the data to be transmit- ted by writing to the e buffer. the user can configure the interrupt enable regis- ter to cause interrupts to occur whenever ?e to f? buffer transfers occur. this allows determination of the allowable time periods to interact with the e buffer. also provided is an ?e to f? inhibit bit. the ?e to f? buffer transfer is disabled whenever the user sets this bit. this may be used whenever ?long? control port interactions are occurring. a flowchart for reading and writing to the e buffer is shown in figure 15. for writing, the sequence starts after a e to f transfer, which is based on the output timebase. if the channel status block to transmit indicates pro mode, then the crcc byte is automatically calculated by the cs8405a, and does not have to be written into the last byte of the block by the host microcontroller. this is also true if the channel sta- tus data is entered serially through the copy/c pin when the part is in hardware mode. control port to aes3 transmitter e 24 words 8-bits 8-bits ab f transmit data buffer figure 14. channel status data buffer structure e to f interrupt occurs optionally set e to f inhibit if set, clear e to f inhibit return write e data wait for e to f transfer figure 15. flowchart for writing the e buffer
cs8405a 36 ds469f2 15.1.2 serial copy management system (scms) in software mode, the cs8405a allows read/mod- ify/write access to all the channel status bits. for consumer mode scms compliance, the host mi- crocontroller needs to manipulate the category code, copy bit and l bit appropriately. in hardware mode, the scms protocol can be fol- lowed by either using the copy and orig input pins, or by using the c bit serial input pin. these options are documented in the hardware mode section of this data sheet. 15.1.3 channel status data e buffer access the e buffer is organized as 24 x 16-bit words. for each word the ms byte is the a channel data, and the ls byte is the b channel data (see figure 14). there are two methods of accessing this memory, known as one byte mode and two byte mode. the desired mode is selected through a control register bit. 15.1.3.1 one byte mode in many applications, the channel status blocks for the a and b channels will be identical. in this situ- ation, if the user reads a byte from one of the chan- nel's blocks, the corresponding byte for the other channel will be the same. similarly, if the user wrote a byte to one channel's block, it would be necessary to write the same byte to the other block. one byte mode takes advantage of the often identical nature of a and b channel status data. when reading data in one byte mode, a single byte is returned, which can be from channel a or b data, depending on a register control bit. if a write is be- ing done, the cs8405a expects a single byte to be input to its control port. this byte will be written to both the a and b locations in the addressed word. one byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes worth of information in 1 byte's worth of access time. if the control port's auto increment address- ing is used in combination with this mode, multi- byte accesses such as full-block reads or writes can be done especially efficiently. 15.1.3.2 two byte mode there are those applications in which the a and b channel status blocks will not be the same, and the user is interested in accessing both blocks. in these situations, two byte mode should be used to access the e buffer. in this mode, a read will cause the cs8405a to out- put two bytes from its control port. the first byte out will represent the a channel status data, and the 2nd byte will represent the b channel status data. writing is similar, in that two bytes must now be in- put to the cs8405a's control port. the a channel status data is first, b channel status data second. 15.2 aes3 user (u) bit management the cs8405a u bit manager has two operating modes: mode 1. transmit all zeros. mode 2. block mode. 15.2.1 mode 1: transmit all zeros mode 1 causes only zeros to be transmitted in the output u data, regardless of e buffer contents. this mode is intended for the user who wants the output u channel to contain no data. 15.2.2 mode 2: block mode mode 2 is very similar to the scheme used to control the c bits. entire blocks of u data are buffered using 2 block-sized rams to perform the buffering. the user has access to the first buffer, denoted the e buff- er, through the control port. it is the only mode in which the user can merge his own u data into the transmitted aes3 data stream. the u buffer access only operates in two byte mode, since there is no con- cept of a and b blocks for user data. the arrange- ment of the data is as follows: bit15[a7]bit14[b7]bit13[a6]bit12[b6]...bit1[a0] bit0[b0]. the arrangement of the data in each byte is that the msb is the first transmitted bit. the bit for the a subframe is followed by the bit for the b subframe.
cs8405a ds469f2 37 16. revision history release date changes pp1 november 1999 1st preliminary release pp2 november 2000 2nd preliminary release pp3 may 2001 3rd preliminary release pp4 june 2002 4th preliminary release pp5 march 2003 5th preliminary release f1 january 2004 final release f2 august 2004 added lead-free device ordering information. table 5. revision history contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of li ability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or techn ologies described in this material and controlled under the "foreign exchange and foreign trade law" is to be exported or taken out of japan. an export license an d/or quota needs to be obtained from the competent authorities of the chinese government if any of the products or technologies described in this material is s ubject to the prc foreign trade law and is to be exported or taken out of the prc. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, life support products or other critical applications (including medical devices, aircraft systems or components and personal or automotive safety or se- curity devices). inclusion of cirrus products in such applications is understood to be fully at the customer?s risk and cir- rus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or cus- tomer?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to ful- ly indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor. purchase of i2c components of cirrus logic, inc., or one of its sublice nsed associated companies conveys a license under the philips i2c patent rights to use those components in a standard i2c system.

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